1. Field of the Invention
The present invention relates to the frequency synchronisation of clocks. Embodiments of the invention relate to frequency synchronisation of clocks over an asynchronous switched network.
2. Description of the Prior Art
It has been proposed to distribute, over an asynchronous switched network, data which is generated at a source synchronously with a reference clock. The data may be distributed to many receivers which process the data independently of each other. However the received data needs to be processed synchronously with a local clock in a receiver and that local clock needs to be synchronous with the reference clock. An example of such data is video. There are other examples of such data. An example of such a network is an Ethernet network. There are other examples of such networks.
A prior proposal demonstrated at NAB 2001 distributed video data over a network. Timing data linking local clocks to a reference clock was distributed over another, separate, network
It is desired to provide synchronisation via the network.
ITU-T Rec H222.0 (1995E) discloses that within the ITU-T Rec H222.01 ISO/IEC 13818-1 systems data stream (i.e. MPEG) there are clock reference time stamps called System Clock References (SCR). The SCRs are samples of the System Time Clock (STC). They have a resolution of one part in 27 MHz and occur at intervals of upto 100 ms in Transport Streams and upto 700 ms in Program Streams. Each Program Stream may have a different STC. The SCR field indicates the correct value of the STC of an encoder at the time the SCR is received at a corresponding decoder. With matched encoder and decoder clock frequencies, any correct SCR value can be used to set the instantaneous value of the decoders STC. This condition is true provided there is no discontinuity of timing for example the end of a Program Stream. In practice the free running frequencies of the clocks will not be matched. Thus there is a need to slave the clock of the decoder to that of the encoder using a Phase Locked Loop (PLL).At the moment each SCR arrives at the decoder it is compared with the STC of the decoder. The difference (SCR-STC) is an error which is applied to a low pass filter and gain stage to generate a control value for the voltage controlled oscillator which is the clock of the decoder.
The system described above uses a synchronous network and locks the absolute time of the decoder clocks to the reference clock.
The present invention seeks to synchronise the frequencies of clocks of data processors linked by an asynchronous packet switched network without requiring infrastructure additional to the network.